"Physical Design for VeSFET-based High-Density Regular Circuits"

Yi-Wei Lin, Ph.D. Defense

September 1st (Wednesday), 11:00am
HFH 4164

Nowadays, the design complexity and fabrication cost increase dramatically with technology advances. One of the key reasons is that the increasing mutual dependencies between the devices with smaller dimensions become more difficult to accout for and abstract. One of the options to reduce designers’ efforts to cope with complex interactions between layout components is to use regular patterns. In this talk, we study the circuit characteristics and describe design methodologies for building circuits from prefabricated high-density arrays of super-regular Vertical Slit Field-Effect Transistors (VeSFETs). The super-regular transistor array along with strictly parallel wire patterns can reduce the mask data volume and lead to better manufacturability and lower fabrication costs. The VeSFET-based high-density regular circuits with comparable performance and power density require only about half the chip area of the circuits designed using the conventional CMOS ASIC flow.

Hosted by: Professor Malgorzata Marek-Sadowska