PhD Defense: "Integrated CMOS Controller for Fast Optical Switching"

Luis Chen

December 17th (Monday), 1:00pm
Elings Hall, Room 1601

The growth in data centers traffic today is demanding more energy efficient way of computing and moving data across servers. Recent advances in silicon photonics open up exciting opportunities to solve the bandwidth limitation both on-chip and off-chip wire interconnects. On-chip photonic interconnects have been proposed to link multi-core systems to create a single logical compute node with terascale processing capability in an energy efficient manner. Within the data center, packet switching network is the preferred way of connecting compute servers because of low latency and high network utilization. Optical packet switching becomes an attractive solution as the demand for bandwidth increases. Traditional electronic network switches approach power consumption limits as data-rates continue to scale to higher. While optoelectronic and MEMS optical network switches have been demonstrated before as solutions, the high costs and power consumption are barriers to mass commercialization. The key to overcoming this barrier is to integrate both active and passive photonic devices with CMOS and take advantage of the economy of scale of mature silicon manufacturing processes and thus lowering the cost while simultaneously enhancing the reliability of optoelectronic systems. In this work, we aim to develop the necessary technologies to show the feasibility of high port-count fast optical switches with nanosecond scale switching time for data center applications.

In this talk, I will present the design of a fully integrated controller designed and implemented in a 0.13um CMOS process. The controller consists of a 2-Channel optical packet header receiver that integrates a novel burst-mode truly differential transimpedance amplifier, limiting amplifier and a burst-mode gated-oscillator based clock and data recovery circuit on the same chip, which also includes an on-chip phased-locked loop to generate the data clock, resulting in an ultra-fast lock time of 13ns, at low power consumption of 43.6mW per channel at 2.5Gbps operation. Second, the design of a low-power, area efficient and adjustable output optical switch fabric driver is presented. The driver enables 3.8ns of switching time when driving a 2×2 optical switch while consuming <150uW of static power and occupies 0.01mm^2 of silicon space. Finally, the design of an automatic power control loop that enables optical gain of up to 10dB is presented. The ability to compensate for optical losses enables the construction of large port count switches that are necessary for data center applications.

About Luis Chen:

photo of luis chen Luis Chen received his B.S. and M.S. in Electrical Engineering in 2006 and 2007 at the University of California, Santa Barbara with emphasis in RF Communication Electronics and Integrated Circuits. Currently, he is pursuing his PhD at UCSB under the supervision of Prof. Luke Theogarajan. His areas of interests are Low-power/high-speed analog and mixed signal integrated circuits, with applications to RF/Optical communication and sensors. In the summers of 2009, and 2010, he interned at GE Energy in Goleta, CA and GE Global Research’s RF and Photonics Lab in Niskayuna, NY respectively. In the spring of 2012, he interned at the Mixed-Signal IP group at Qualcomm's QCT division in San Diego, CA. Luis is the recipient of the IEC William L. Everitt Award of Excellence in 2006, Best Teaching Assistant in 2008 and 2009, and UCSB Institute for Energy Efficiency's Holbrook Foundation Fellowship in 2011-2012.

Hosted by: Luke Theogarajan