"IEE Seminar: Power Management from Smartphones to Data Centers"

Thomas Wenisch, Professor, CSE, University of Michigan

February 13th (Wednesday), 4:00pm
Engineering Science Building (ESB), Room 1001

Power has become a first-class design constraint in computing platforms from the smartphone in your pocket to warehouse-scale computers in the cloud. Historically, semiconductor innovation has repeatedly provided more transistors (Moore’s Law) for roughly constant power per chip by scaling down supply voltage each generation. Unfortunately voltage scaling has ended due to stability limits and chip power densities are increasing each generation on a trajectory that outstrips improvements in the ability to dissipate heat. To continue to extract value from Moore’s Law, we need to find system-level approaches to improve efficiency and deliver more performance within tight energy, power, and thermal constraints.

In the first part of this talk, I will discuss Computational Sprinting, a technique to improve the responsiveness of smartphone platforms by transiently exceeding sustainable thermal limits — firing up numerous `dark silicon’ cores to complete a sub-second burst of computation while buffering the resulting heat in a phase change material embedded in the chip’s heat sink. Then, I will shift focus to warehouse-scale computing to discuss power management in online data intensive services. These applications, such as web search, social networking, and ad serving, must process terabytes of data in interactive time scales, making them a challenging target for power management.

About Thomas Wenisch:

photo of Thomas Wenisch Thomas Wenisch is the Morris Wellman Faculty Development Assistant Professor of Computer Science and Engineering at the University of Michigan, specializing in computer architecture. Tom's prior research includes memory streaming for commercial server applications, store-wait-free multiprocessor memory systems, memory disaggregation, and rigorous sampling-based performance evaluation methodologies. His ongoing work focuses on computational sprinting, data center architecture, energy-efficient server design, and multi-core / multiprocessor memory systems. Tom received an NSF CAREER award in 2009, three papers selected in IEEE Micro Top Picks, and Best Paper Awards at HPCA 2012 and ISPASS 2012. Prior to his academic career, Tom was a software developer at American Power Conversion, where he worked on data center thermal topology estimation. He is co-inventor on six patents. Tom received his Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University.

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