PhD Defense: "Scalable and High Quality Algorithm Design For High Level Synthesis"

Wei Tang

March 10th (Monday), 11:00am
Harold Frank Hall (HFH), Rm 4164

The semiconductor industry has been pushing higher and higher transistor density to support systems with increasing complexity. While this enables power savings and performance opportunities, it poses serious scaling challenges as well. Efficient schedule and map operations along with data movement and storage management on a hardware platform is the key to high quality digital system design. The de-facto design flow uses a divide and conquer approach. It relies on multiple abstraction levels, such as task and operation levels, to break the problem down. A multi-level abstraction is necessary because increasing system complexity outpaces scalability improvements of existing scheduling and mapping algorithms. This work discusses the fundamental reasons for scalability and quality issues of existing approaches. It further presents a hierarchical analysis framework that can dramatically increase the scalability of existing state-of-the-art scheduling and mapping algorithms while maintaining the same or superior quality. The hierarchical framework does not rely on existing application hierarchy, thereby relaxing the requirement of advanced design experience. Instead, it automatically builds a hierarchical representation from a flat specification, and uses hierarchy to globally guide the scheduling and mapping process. The framework gradually explores the solution space and uses special hierarchical constraints that are tight enough to control algorithm complexity while allowing cross-boundary optimization. The presented scheduler runs an order of magnitude faster than state-of-the-art algorithms while generating better, higher performance solutions. This dramatic scalability improvement blurs the boundary between abstraction levels to exploit potential performance gains. The framework handles practical, real-world applications with 10,000 operations. It enables high quality heuristic scheduling and mapping algorithms for applications which were previous considered untenable.

About Wei Tang:

photo of wei tang Wei Tang is a Ph.D candidate in the Department of Electrical and Computer Engineering (ECE) at University of California, Santa Barbara (UCSB). His Ph.D advisor is Prof. Forrest Brewer. He received his M.S from ECE, UCSB in 2009 and B.S from Beijing University of Posts and Telecommunications in 2007. He joined Prof. Forrest Brewer's group in 2009. His research interests include high level synthesis and system level optimization.

He won the outstanding TA award from ECE, UCSB in 2009 and 2013. He was the recipient of the ECE Dissertation Fellowship in Spring 2013.

Hosted by: Professor Forrest Brewer