PhD Defense: "Enhancing the Capability of Constrained Random Test Program Generators via Learning and Test Program Filtering"

Vinayak Kamath

September 25th (Thursday), 10:00am
Harold Frank Hall (HFH), Room 4164

Functional verification of RTL is one of the primary and most time consuming tasks of microprocessor design. However, designs cannot be completely verified due to their large size and strict time-to-market restrictions. Being more scalable, simulation-based verification has become the mainstay of functional verification. A majority of the randomly generated tests used for design simulation are, however, redundant. This work proposes a two-step approach to achieve faster verification closure.

We propose a novel methodology to improve the effectiveness of one test generator with respect to another. First, we evaluate the effectiveness of using a legacy test generator used at AMD and quantify its verification performance. We explore the differences in the design and capabilities between the legacy test generator and AMD’s latest in-house x86 ISA-based test generator. We then proceed to gather experimental evidence to support our understanding. We propose to utilize external test filters to overcome the limitations of the latest exerciser.

We develop a test filtration approach that is independent of the test generator, to filter out ineffective tests prior to RTL simulation. We achieve this by using ISA simulation traces. We find that using a combination of ISA simulation traces and microarchitectural models is necessary to cover a wider range of coverpoints. Our work shows that by using implementation specific details for extrapolating test behavior information present in simulation traces, we can compensate for microarchitecture agnostic test generation and consequently improve the effectiveness of a test generator without modifying its design. The proposed approach expedites coverage closure by providing precise control over random test behavior. Experimental results based on the latest AMD multi-core processor design are presented to demonstrate the feasibility of our proposed approach.

About Vinayak Kamath:

Vinayak Kamath graduated with a bachelors degree in Electrical and Computer Engineering from National Institute of Technology, Karnataka in 2008. He received his masters in Electrical and Computer Engineering at University of California, Santa Barbara in 2012.

During the course of his Phd, he has worked with several key semiconductor companies including Intel, Oracle (Ex Sun Microsystems) and Advanced Micro Devices (AMD). He won the Executive Spotlight Award in 2014 at AMD for his contribution to their microprocessor core verification. His research interests are constraint based verification, machine learning, random test generation and post-silicon validation.

Hosted by: Professor Li-C Wang