PhD Defense: "Design, Fabrication, and Characterization of High Performance III-V nMOSFETs for VLSI Beyond Si-CMOS Scaling Limit"

Sanghoon Lee

October 24th (Friday), 2:00pm
Elings Hall, Room 1601

The revolution of the silicon VLSI technology during the past several decades has been ultimately driven by the goal of miniaturization, which leads to an increase in switching speed as well as integration density and a reduced power consumption. As the device size in VLSI has nearly approached its physical limit in the last few years, the industry and academia have been actively evaluat- ing some of the emerging technologies as an alternative to the classical Si-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). Among them, III- V compound semiconductor based transistors are being considered as one of the viable candidates for the future VLSI at scaling generations beyond 7 nm-node. The low electron effective masses in III-V semiconductor materials (i.e. InGaAs) provide superior electron transport properties such as high electron velocity and mobility. According to ballistic transport calculation results, InGaAs based chan- nel devices can potentially exhibit a 1.5 times higher drive current (> 2 mA/μm) even at a lower supply voltage (VDD < 0.7 V) over the Si counterparts. Thus, for faster and smaller integrated circuits with reduced power consumption, III-V based transistors may be the solution to VLSI beyond the physical limitations encountered in scaling of the conventional Si-based MOSFETs. In order to achieve device performances close to the idealized target, several critical requirements must be met. Firstly, the high-k gate dielectric must be ultra-thin (equivalent oxide thickness < 0.5 nm) and nearly defect-free (interfacial trap density < 1012 /cm2-eV). Hence, any high damage inducing process is not allowed, and surface passivation techniques must be carefully developed. Secondly, the epitaxial layer design should be optimized, especially since there is a trade-off between the on- and off-state performances associated with the channel thickness as well as the indium content. Thirdly, source/drain (S/D) regions must be very heavily doped in order to avoid potential source starvation and to minimize the contact resistivity. Furthermore, this heavy doping must not extend more than 1-2 nm below the depth of the channel to avoid degradation of the short-channel characteristics. Lastly, the device must be highly scalable. To satisfy the tight integration density requirement in VLSI, the gate length and contact pitch should be less than 14 nm and 30 nm, respectively. To achieve this, S/D must be very close to the gate, i.e., self-aligned. With the abovementioned key design considerations in mind, InGaAs based raised S/D quantum-well MOSFETs have been developed using S/D regrowth as well as the substitutional-gate (i.e. gate-last) scheme. By adopting this device structure, any process-induced damage at the semiconductor/dielectric interface is reduced, and heavily doped S/D is readily formed in a self-aligned manner. Recently, III-V MOSFETs with a record performance have been reported through this work, by implementing sub-1 nm EOT high-k dielectrics with a low interface trap density and adopting an optimized device structure to suppress the off-state degradation at the short channel lengths. A device with a gate length of 18 nm has shown a 3.0 mS/μm peak transconductance (gm) at VDS = 0.5 V, which is the highest peak gm from any reported field-effect transistors to date. A device with an ultra-thin channel and thick vertical spacers at a gate length of 25 nm exhibits an excellent performance in both the on-state and off-state, featuring 2.4 mS/μm peak gm, 77 mV/decade minimum subthreshold swing at VDS = 0.5 V, 76 mV/V drain-induced barrier lowering, and 500 μA/μm on-current at a fixed 100 nA/μm off-current and VDD = 0.5 V. This is the highest on-current from any reported III-V-based MOSFETs and is comparable to state-of-the-art Si-Fin- and nanowire-FETs. In comparison with calculation results obtained from a ballistic FET model, it has been found that the fabricated devices with Lg = 25 nm are operating nearly in the ballistic limit.

About Sanghoon Lee:

Sanghoon Lee received the M.S degree on low frequency noise characterization for CMOS devices in the Department of electrical and computer engineering at Seoul National University, Seoul, Korea, in 2009. He is currently pursuing the Ph. D. degree with the Department of Electrical and Computer Engineering, University of California, Santa Barbara, USA. His current research interests include fabrication and characterization on III-V MOSFETs for VLSI applications.

Hosted by: Sanghoon Lee, Rodwell Group