PhD Defense: "The Interconnect of Things in Multicore Architectures"

Jia Zhan

June 3rd (Friday), 10:00am
Harold Frank Hall (HFH), Rm 4164

The last few years we have witnessed a growing trend of accommodating many processing elements (such as cores, caches, etc.) in a single chip, both in general-purpose processors and in embedded systems. Conventional shared-memory multi-core design adopts a single bus with limited bandwidth as the communication backbone. Consequently, the bus bears enormous strain and even becomes the performance bottleneck due to frequent packet transmission, leading to recent many-core chips interconnected with sophisticated Network-on-Chip (NoC). Such systems have routers at every node, connected to neighbors through short links, while multiplexing packets flows at each router to provide high scalable bandwidth.

Most of the prior research in NoC focused on optimizing NoC standalone, specifically its topology, routing algorithm, arbitration strategy, or flow control policy. In this talk, we architect on-chip interconnect for many-core systems, with customized network architecture to integrate various emerging hardware technologies while satisfying the demand of software applications. Specifically, from a hardware perspective, emerging heterogeneous CPU-GPU multicores, non-volatile memories (NVM), and 3D-stacked memories are transforming the traditional computing power and memory subsystem. As a result, we should design NoC as the communication backbone to connect all these components and build a scalable system. From an application perspective, real-time embedded applications and general purpose commercial desktop workloads pose different performance requirements to the underlying hardware system, and thus the NoC should be provisioned to provide just enough power to support these workloads. Additionally, emerging big data workloads, especially in-memory computing applications, not only require more computing power to process data in parallel, but also stress the memory or storage system for fast data retrieval. Consequently, the intensive memory traffic stresses the memory fabric, calling for a scalable network design to satisfy workload demand.

This defense will discuss different NoC architectures, with a focus on two topics: (1) Designing NoC for heterogeneous CPU-GPU multicores, and (2) designing memory network for in-memory computing applications.

About Jia Zhan:

photo of jia zhanJia is currently a 5th year PhD student in Computer Engineering at UCSB. Before transferring to UCSB with Dr. Yuan Xie, he spent three years as a PhD student in Computer Science & Engineering at the Pennsylvania State University. Jia received his B.S. degree from Harbin Institute of Technology in 2011. His research interests include a broad range of computer system architecture, especially Network-on-Chip for (heterogeneous) many-core processors, emerging non-volatile memories, and large-scale datacenter networks. During his PhD, Jia has done summer internships with Baidu USA R&D center, HP Labs, and ETH Zurich, Switzerland.

Hosted by: Professor Yuan Xie