PhD Defense: "Abusing Hardware Race Conditions to Perform Useful Computation"

Advait Madhavan

September 13th (Tuesday), 11:00am
Elings Hall (CNSI), Rm 1605

We propose a novel computing approach, called “Race Logic”, which utilizes a new data representation to accelerate a broad class of optimization problems, such as those solved by dynamic programming algorithms. The core idea of Race Logic is to deliberately engineer race conditions in a circuit to perform useful computation. In Race Logic, information, instead of being represented as logic levels (as is done in conventional logic), is represented as a timing delay. Computations can then be performed by observing the relative propagation times of signals injected into a configurable circuit (i.e. the outcome of races through the circuit).

In this talk I will introduce Race Based computation and talk about multiple VLSI implementations. We first begin by considering a synchronous approach, which uses simple clocked delay elements. Though this synchronous implementation outperforms highly optimized conventional implementations of the well-studied, DNA sequence alignment problem, its third order energy scaling with problem size and limited dynamic range of timing delays are its major pitfalls. Next, in the search for energy efficiency, we study asynchronous designs in order to understand the performance trade-offs and applicability of this new architecture. Finally, I will present the results of a prototype asynchronous Race Logic chip and demonstrate that Race-Based computations can align up to 10 million 50 symbol long DNA sequences per second, about 2-3 orders of magnitude faster than the state of the art.

About Advait Madhavan:

Advait Madhavan received his B.Tech. in Instrumentation and Control engineering from Netaji Subhas Institute of Technology (NSIT) in New Delhi, in 2010 and his M.S. in Electrical and Computer Engineering from UCSB in 2014. His main research focuses on novel architectures for computation using temporal information representation techniques. His research interests span integrating emerging technologies with CMOS, neuromorphic VLSI design, ASIC based hardware acceleration and approximate computing.

Hosted by: Professor Dmitri Strukov