PhD Defense: "Energy, Lifetime and Variation-Aware ReRAM Architectures for Memory and Neuromorphic Computing Applications"

Miguel Lastras

May 23rd (Tuesday), 5:00pm
Harold Frank Hall (HFH), Rm 4164 (ECE Conf. Rm.)

photo of miguel lastras
Resistive random-access memory (ReRAM) based on two-terminal “memristive” devices has been recognized by the International Technology Roadmap for Semiconductors (ITRS) as an excellent candidate for the next generation of non-volatile, high-density, and high-performance memories. The ITRS, however, has also realized that ReRAM still suffers from significant limitations, namely, high energy consumption (due to the sneak-path problem), limited endurance, and large cycle-to-cycle (C2C) and device-to-device (D2D) variations. While these limitations have been traditionally addressed via device-level improvements, in my thesis I present architectural solutions to such limitations.

In particular, to address the sneak-path problem and limited endurance issue, I propose a hybrid reconfigurable architecture, called HReRAM, in which we take advantage of the fact that a complementary resistive switch (CRS) can behave both as a memristor and as a CRS. By dynamically keeping frequently accessed regions of the memory in the memristive mode and others in the CRS mode, our hybrid memory offers the performance and endurance benefits of a memristor-based memory, and the low energy consumption of a CRS-based memory.

To address the D2D and C2C variability issues, we propose a memory cell comprised of two memristive devices and a field-effect transistor, and present an information encoding scheme that results in a non-destructive readout operation that is more robust and less prone to the D2D and C2C variations.

Finally, I will present a high-bandwidth dot-product engine, called 3D-DPE, in which we use a current-based analog approach to compute the dot-product operation in a single clock step. Through a collaborative effort, we experimentally demonstrated the core concept of 3D-DPE by monolithically fabricating two layers of memristive crossbars on top of a standard CMOS chip, and we illustrated its functionality by performing physical measurements, with orthogonal signals applied in different layers under different conductance values.

About Miguel Lastras:

Miguel is a PhD Candidate in the Electrical and Computer Engineering Department at the University of California, Santa Barbara. He received his B.Sc. degree in Engineering Physics and M.Sc. degree in Applied Sciences from the Universidad Autonoma de San Luis Potosi, Mexico, in 2008 and 2010, respectively; and a M.Sc. in Computer Engineering from University of California, Santa Barbara in 2012. His research interests include the architectural aspects of low-power crossbar-based memristive memories and its 3D monolithic integration with standard CMOS processes.

Hosted by: Professor Tim Cheng