PhD Defense: "Assessing VeSFET Monolithic 3D Technology in Physical Design, Dynamic Reconfigurable Computing, and Hardware Security"

Ping-Lin Yang

December 5th (Tuesday), 4:00pm
Elings Hall, Room 1601

With the continuous demands on integrating more functions and devices on a single chip, the technology has been evolving along the scaling path for decades. The transistor feature size has been scaled down from μm order toward 7nm, 5nm, and even below. Conventional MOSFET / FinFET devices are approaching physical limitations. It is extremely difficult to integrate more devices solely by further transistor scaling. Besides scaling, 3D integration technologies offer attractive features. By stacking devices, it increases device density and reduces wire length, which implies better PPA (performance, power consumption, and area). However, the increased power density and the extra overhead of inter-tier connections are significant concerns for deploying 3D integration technologies. For sustaining future technology growth, it is expected that fundamental changes of device structure are required. Vertical Slit Field Effect Transistor (VeSFET) is a novel transistor with unique structure and characteristics. It is two-side accessible and low power consuming, which is 3D integration friendly.

This work investigates VeSFET technology and proposes unique and powerful applications, which are not feasible using MOSFET technologies. This talk first provides an introduction of VeSFET technology and followed by a monolithic 3D physical design assessment. The IR-drop on power delivery network and clock distribution network characteristics are assessed. Then, unique applications using VeSFET monolithic 3D technology are presented. A fast, fully verifiable, and hardware predictable ASIC design methodology using 3D FPGA is proposed, the performance comparison of VeSFET 2D and 3D FPGA shows that the 3D FPGA is faster, smaller, and consumes less power. Then, a high performance dynamic reconfigurable architecture is proposed using VeSFET fast reconfigurable 3D FPGA-based accelerator. The system level performance evaluation shows significant improvement over the system with no accelerator or with conventional FPGA-based accelerator. Toward trustworthy hardware designs, a secure split-fabrication method using VeSFET is proposed for addressing hardware security concerns, such as piracy prevention, hardware Trojan prevention and detection. Any Trojan insertion or design tampering can be easily detected. This presentation will give a whole picture of VeSFET technology from device to system levels.

About Ping-Lin Yang:

Photo of Ping-Lin Yang Ping-Lin Yang received his B.S. and M.S. degrees both in Electrical Engineering from National Tsing Hua University, Hsinchu, Taiwan, in 2005 and 2007. In the Fall of 2013, he joined VLSI CAD Lab, advised by Professor Malgorzata Marek-Sadowska, at the Department of Electrical and Computer Engineering, University of California, Santa Barbara. Prior to his Ph.D. study and during 2007 to 2013, he was a R&D Principal Engineer with TSMC, Hsinchu, Taiwan, dedicated to chip design technology developments especially for high performance embedded CPUs. In the Summer of 2015, he was with IBM Research, Albany, NY, for the researches of post-7nm and monolithic 3D technologies. His publications include 17 conference and journal papers, and 12 patents (10 United States, 1 Korea, and 1 China patents).

Hosted by: Professor Malgorzata Marek-Sadowska