Events

"Accelerating Logic Computing"

Luca Amaru, Senior II R&D Engineer, Synopsys Inc.

March 14th (Wednesday), 11:00am
Harold Frank Hall (HFH), Rm. 4164 (ECE Conf. Rm.)


During the last six decades, computer technology has been moving forward at an incredible pace. From 1958 to 2018, computing systems have seen a 1 trillion-fold increase in performance and a commensurate increase in the complexity of tasks they can solve. This exceptional progress is reality thanks to the continuous research in device technology and computing models. In this talk, I show how new and technology-aware logic models can provide further acceleration of computing in present and future technologies. First, I illustrate the enabling role of native logic abstractions in the study of emerging nanotechnologies, ranging from enhanced functionality devices to new computational paradigms. Second, I present technology-driven models in logic manipulation algorithms and data-structures, pushing the solving limits for hard problems in computer science. Finally, I introduce a cloud-scale FPGA accelerator for Boolean SATisfiability (SAT), combining algorithmic and architecture innovations, capable of determining hard SAT problems that do not find answer with state-of-the-art methods.

About Luca Amaru:

Photo of Luca Amaru Luca Gaetano AmarĂ¹ received the B.S. and M.S. degrees in electronic engineering from the Politecnico di Torino, Turin, Italy, in 2009 and 2011 respectively, and the Ph.D. degree in computer science from the Swiss Federal Institute of Technology Lausanne (EPFL), Lausanne, Switzerland, in 2015. He is Senior II R&D Engineer in the Design Group of Synopsys Inc., Mountain View, CA, USA, where he is responsible for designing efficient data structures and algorithms for EDA. Previously, he was research assistant at EPFL and visiting researcher at Stanford University. His current research interests include logic manipulation, with emphasis on optimization and SAT, accelerating logic reasoning engines, at both algorithmic and hardware implementation levels, and beyond CMOS design & nanotechnology exploration. Dr. Amaru is author or co-author of 75+ technical articles. His awards and achievements include: Synopsys Leading Edge Talent Program, 2017, Best Paper Award Nomination in TCAD, 2017, EDAA Outstanding Dissertation Award, 2016, Best Presentation Award at FETCH conference, 2013, Best Paper Award Nomination at ASP-DAC conference, 2013, and others.

Hosted by: UCSB CE Program