"Multi-layer Graphene Process for Interconnect and Electrode"

Kazuyoshi Ueno, Professor, Department of Electronic Engineering, College of Engineering Shibaura Institute of Technology (SIT)

June 12th (Tuesday), 2:30pm
Harold Frank Hall (HFH), Rm 4164 (ECE Conf. Rm.)

Since graphene has a long mean free path and high current density resistance, it is expected as a material to break through the limit of Cu in nano-interconnects. It is also expected to improve thermal stability of devices and as a diffusion barrier material because of its high melting point. On the other hand, in order to actually apply graphene to devices, it is necessary to deposit a film with good crystallinity at low temperature and also to increase the number of carriers to reduce the resistance. In this presentation, as a method of film formation, we introduce a process which can improve crystallinity at low temperature by using the action of electric current in addition to heat. In addition, solid phase precipitation (SSP) without transfer is introduced as a film deposition method which has high affinity with current device manufacturing. A thin multilayer graphene (MLG) film can be formed by the cap layer which suppresses the agglomeration of the catalyst during SSP. We also introduce bromine intercalation and MoCl5 intercalation as a doping method. MoCl5 intercalation has an advantage in its stability in a small pattern compared to other FeCl3 and Br. The characteristics of MLG/GaN diode deposited by solid phase deposition method are also reported.

About Kazuyoshi Ueno:

photo of kazuyoshi uenoProfessor Kazuyoshi Ueno received his Bachelor of Engineering, Master of Engineering, and Doctor of Engineering in 1982, 1984, and 1991, respectively from Tohoku University, Sendai, Japan. He joined NEC Corporation in 1984, and engaged in research of high performance GaAs MESFET for super-computers until 1991, He engaged in process development for interconnect technologies such as Cu interconnection from 1992 to 2006 as a Senior Process Engineer, Manager, and Chief Engineer. He pioneered research on Cu interconnect at NEC, and it was put into practical use for the first time as an LSI for the Earth Simulator. In 2006, he moved to Shibaura Institute of Technology (SIT) as a professor. He has been working on advanced processes for interconnect and metallization such as graphene in SIT. He is a member of JSAP and IEEE.

Hosted by: Professor Kaustav Banerjee