Events

PhD Defense: "CMOS-compatible Doped-Multilayer-Graphene for Next-Generation Interconnects, Passives, and Monolithic 3D ICs"

Junkai Jiang

August 30th (Friday), 10:00am
Harold Frank Hall (HFH), Rm 4164 (ECE Conference Rm)


On-chip metal interconnects that connect billions of transistors and other active devices in modern integrated circuits (ICs) play a dominant role in determining their speed and energy-efficiency. As the interconnect dimensions scale down to sub-20 nm, conventional interconnect materials, such as Cu, suffer from significant size-effects, leading to a strongly non-linear increase in interconnect resistance, which increases self-heating, degrades electromigration (EM) reliability, and thereby limits their current-carrying capacities. Other metals, including Co, offers improvement in reliability w.r.t. Cu, but cannot meet the current-carrying capacity requirements at sub-10 nm dimensions and do not offer any benefits in terms of energy-savings. To address such fundamental challenge, in my doctoral research, low-dimensional materials, including multilayer graphene (MLG), and graphene nanoribbon (GNR), which are known to exhibit high breakdown current density and electrical conductivity with adequate intercalation doping, are designed, fabricated, and demonstrated to be superior to all conventional metals including Cu. In particular, doped-MLG is identified as a preferred replacement for conventional metals in the passive back-end-of-line (BEOL) elements, like wires and inductors.

This presentation will begin with doped GNR (DGNR) interconnect modeling and design at the circuit-level. Carrier transport in graphene and DGNR is studied and a distributed RLC compact model, which accounts for intercalation doping, quantum capacitance, and kinetic inductance effect, is developed and implemented in Verilog-A. Guided by these simulations, the DGNR is further demonstrated experimentally by a subtractive etching process, with FeCl3 intercalation dopants (Nano Letters 2017). Based on the experiments, it is shown that DGNR interconnects can offer >20% performance improvement (delay per unit length at the local level) and 25%/72% energy efficiency improvement at the local/global level, compared with Cu. Detailed reliability characterization is also carried out to understand the nature of the failure mechanism in DGNR wires (IRPS 2017).

Furthermore, to address the large-scale manufacturability and the critical BEOL thermal budget issue, a unique CMOS-compatible transfer-free graphene synthesis method is developed, and DGNR interconnects down to 20-nm in width are demonstrated, with >50x current-carrying capacity improvement and comparable electrical conductivity, w.r.t. Cu, and even higher electrical conductivity compared with Co and Ru (IEDM 2018). A BEOL-compatible vertical via/contact design and process scheme is also proposed and demonstrated experimentally with multi-level MLG wires, showing better circuit performance and supreme reliability against self-heating and electromigration, making DGNR an ideal candidate for sub-10 technology nodes.

The developed DGNR technology can also be exploited to build nano-inductors that exploit the “kinetic inductance” of graphene at room temperature leading to a significant increase in the inductance density, and thereby, leading to scaling of inductors that has been a fundamental bottleneck (Nature Electronics 2018). The talk will end with an exploratory analysis of monolithic 3D (M3D) integration incorporating atomically-thin 2D-materials-based active devices and DGNR interconnects. I will present a summary of the merits of M3D with 2D materials, in terms of overcoming the major drawbacks of current 3D-ICs, including low thermal process budget, inter-tier signal delay, chip overheating and inter-tier electrical interference problems. The analysis has revealed that the 2D-based M3D integration can offer >10-folds higher integration density compared with through-silicon-via (TSV)-based 3D integration, and >150% integration density improvement w.r.t conventional M3D integration (IEEE J-EDS 2019). Therefore, 2D semiconductors and DGNR interconnects provide a better platform, w.r.t. bulk materials (such as Si, Ge, GaN, etc.), for realizing ultra-high-density M3D-ICs for next-generation electronics.

About Junkai Jiang:

Junkai Jiang is a Ph.D. candidate and Graduate Student Researcher in the Nanoelectronics Research Laboratory (NRL), Department of Electrical and Computer Engineering at University of California, Santa Barbara, advised by Prof. Kaustav Banerjee. His doctoral research is focused on the design, modeling, and synthesis of graphene-based interconnects and passives, as well as exploration of monolithic 3D integration with two-dimensional materials. His graphene nanoribbon interconnect compact model (available on nanoHUB) has been widely used by the worldwide research community. His IEDM 2018 article describing a CMOS-compatible doped-multilayer graphene process was one of only two papers included in the first annual “IEDM Highlights” section of an issue of the high profile journal Nature Electronics. He is a recipient of the prestigious IEEE Electron Devices Society Ph.D. Fellowship in 2018, awarded each year to a single Ph.D. student from the entire Americas, and the Best Student Paper Award of 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified (S3S) Conference.

Hosted by: Professor Kaustav Banerjee