Dec 18 (Fri): "Analysis and Design of Precision Timing Circuits using Pulse Mode Event Signaling," Prashansa Mukim, ECE PhD Defense
Timing is an integral part of most VLSI design applications such as clocking, analog-to-digital and digital-to-analog conversion, RF communication, clock and data recovery, time-based metrology and neuromorphic computing. The performance, precision and silicon footprint of timing circuits driving these systems, as well as the energy cost associated with distributing timing and maintaining a notion of global coherence play a crucial role in quantifying the success of these designs. The emergence of new computing architectures and advanced integration techniques have more so necessitated novel timing strategies appropriate for the physical scale of the system being timed.
In this talk, I will present analytical frameworks and circuit solutions to a host of timing problems that are applicable to systems of largely varying scales. The underlying circuits for all these solutions are pulse mode and built using a logic family of pulse gates that use atomic pulses to encode both, data and the time of arrival of data. These gates utilize local negative feedback loops leading to interesting dynamic behavior that is exploited in the design of low-noise closed loop timing circuits.
In the first part of this talk, Collective Pulse Oscillators (or CPOs), the simplest closed loop pulse gate circuits will be presented that achieve figures of merit better than conventional ring oscillators, while also providing precise clock phases much finer than the delay of a typical gate in a given technology. The noise analysis of CPOs will be based on a time-domain analytical model, which will be expanded into a rapid behavioral simulator. Measurement results for different diameter CPOs implemented in 130 nm technology will be presented and used to validate the analytical model. Next, complex CPO topologies that improve the high-frequency stability of loop-connected CPOs will be presented and it will be shown how such structures can be used to implement timing distribution networks that utilize distributed feedback to enhance the accuracy of the timing source itself. Measurement results for a 5.5 GHz low-jitter transmission-line stabilized pulsed wave oscillator implemented in 130 nm that provides 12-full-swing clock phases with a duty cycle of approximately 25% will also be presented.
In the second part of this talk, I will present Multi-Wire Phase Encoding (MWPE), a transition signaling strategy suitable for on-chip/on-interposer links connecting globally asynchronous modules. These links are aimed at reducing the energy cost of moving data across a large scale SoC or NoC, which is known to be orders of magnitude higher than the cost of computation. MWPE, by encoding data in the time correlated switching of multiple signaling wires allows very high-bandwidth data transmission on band-limited and lossy on-chip wires, with PLL/DLL free data recovery, thus not incurring any static power consumption. Theoretical and practical bandwidth limits for MWPE will be derived and link performance in 22 nm FDX technology will be presented. Finally, methods of implementing low cost time-domain linear filters that utilize precise clock phases to reduce timing noise originating from systematic noise sources will be presented.
Prashansa Mukim received her B.E in Electronics and Communication Engineering from Netaji Subhas Institute of Technology (NSIT), New Delhi in 2013, and her M.S. degree in Electrical and Computer Engineering from the University of California, Santa Barbara in 2017. She is currently a Ph.D. candidate in the ECE department at UCSB and is advised by Professor Forrest Brewer. Her research interests include timing circuits, time-based communication and computation strategies, neuromorphic computing and the applications of pulse-mode signaling.
Hosted by: Professor Forrest Brewer
Submitted by: Prashansa Mukim <firstname.lastname@example.org>