Jul 1 (Wed): "Interconnect Architecture Design for Emerging Integration Technologies," Itir Akgun, ECE PhD Defense

Date and Time
Zoom Meeting: https://ucsb.zoom.us/j/8043497848 (Password: 7211473)



As Moore’s Law slows down, new integration technologies emerge, such as 3D integration, silicon interposer-based 2.5D integration, and most recently, monolithic 3D integration. In addition to offering performance, bandwidth, and energy improvements due to shorter wirelength, emerging integration technologies pose new opportunities, challenges, and targets for interconnect design. Meanwhile, interconnect has become an increasingly crucial design target due to hardware, such as increasing heterogeneity and move to chiplet-based systems, and software trends, with memory-bound and data-intensive applications, putting more pressure on the communication system which significantly impacts the system performance. Due to these reasons, our work focuses on designing interconnect architecture for emerging integration technologies, as interconnects and communication fabric increasingly take the center stage in architecture design in post-Moore era.

In this talk, we introduce our work on interconnect architecture design for various emerging integration technologies, following the trends in hardware and software domains. First, targeting emerging data-intensive workloads with high memory capacity and bandwidth requirements, we propose scalable, low latency, high bandwidth, and low energy network-on-chip architecture designs for 3D-stacked memories, called memory networks. Next, following the advances in silicon interposer-based 2.5D integration, we propose a network-on-chip chiplet for intellectual property reuse, as a communication chiplet for future chiplet-based heterogeneous SoCs.  Lastly, we provide design space exploration for interconnect architectures for monolithic 3D integration, to discover trade-offs and provide guidelines for network-on-chip design under unique interconnect characteristics.


Itir Akgun is a PhD candidate in Computer Engineering advised by Professor Yuan Xie. Her main research interests within computer architecture are interconnect architecture, on-chip and on-package networks, memory networks, emerging 3D/2.5D integration technologies, and domain-specific acceleration. She received her B.S. in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign in 2014, and her M.S. in Electrical and Computer Engineering at the University of California, Santa Barbara in 2015.

Hosted by: Professor Yuan Xie

Submitted by: Itir Akgun <iakgun@ece.ucsb.edu>