Sep 23 (Wed): "Cost-Driven Integration Architectures for Multi-Die Silicon Systems" Dylan Stow Randall, ECE PhD Defense

Date and Time
Zoom Meeting
Meeting ID: 276 344 5901
Password: 01248


The consistent cadence of Moore's Law has long driven improvement in compute performance by delivering increased transistor counts at equivalent cost per area. However, as transistor process technology advances into the single-digit nanometer nodes, it is evident that the required fabrication complexity has jeopardized the rate of transistor-size reduction as well as the cost-per-transistor. To continue increasing transistor counts without increasing manufacturing cost, an alternative solution is to utilize new multi-die packaging methods.

Manufacturing yields can be improved by fabricating multiple smaller ``chiplets'' and validating each one before integrating them together, thus reducing the cost per functional system or increasing the number of transistors at the same cost. Additionally, multi-die chiplet systems provide opportunities for heterogeneous process integration and design reuse that can further reduce cost.

However, partitioning a monolithic chip into multiple chiplets introduces several new design considerations. First, which packaging technology, such as 2.5D interposer integration or Through-Silicon-Via (TSV) 3D stacking, is best suited to integrate a given multi-die system? Second, how can a partitioned chiplet system effectively communicate between dies without introducing bandwidth bottlenecks or excessive communication latency? Third, how should a system be partitioned across chiplets of various heterogeneous process technologies? Although many industry roadmaps are making clear transitions towards multi-die system design, academic research has made few strides towards answering these questions with respect to the range of modern packaging advances.

This talk will address these challenges by providing methodology and analysis of the cost, power, and communication performance of several of the most promising packaging opportunities, including stacked 3D TSV integration, passive and active 2.5D interposer integration, and sequential monolithic 3D fabrication. First, manufacturing yield and cost models will be presented to demonstrate the cost benefit and overheads of multi-die integration strategies. Next, these models are expanded with thermal-analysis-driven packaging and cooling costs to provide insight into the overheads of increased circuit density. Additionally, a detailed investigation into the power density of modern 3D-stacked dynamic memory is performed to illustrate the challenges of high-density packaging. Based on these thermal-density concerns, reduced-density interposer-based systems, using either passive or active silicon interposer substrates, are investigated to develop effective Network-on-Interposer topologies.

Finally, the communication requirements for future high-density Monolithic 3D systems are investigated and used to develop improved Network-on-Chip topologies that meet the unique requirements of sequential fabrication technologies.


Dylan Stow Randall is a PhD candidate in Computer Engineering and a member of Professor Yuan Xie's Scalable Energy-efficient Architecture Lab (SEAL). His primary research interest is the development of efficient architectures for multi-die integrated systems with advanced 2.5D and 3D packaging. His other work includes the utilization of advanced packaging techniques for hardware security, and the usage of machine learning for circuit design automation and medical diagnosis. Dylan's previous work at AMD has contributed to the Zen CPU core, High-Bandwidth Memory power projection, and future CPU products. He received his B.S. in Engineering at Harvey Mudd College in 2013 and his M.S. in Electrical and Computer Engineering at the University of California, Santa Barbara in 2017.

Hosted by: Professor Yuan Xie 

Submitted by: Dylan Stow Randall <>