Jul 29 (Thu) @ 12pm: "Triple-heterojunction (3-HJ) TFETs Design and Fabrication," Hsin-Ying Tseng, ECE PhD Defense

Date and Time
Location
Zoom Meeting - Meeting ID: 841 9414 4015 | Passcode: 598271

https://ucsb.zoom.us/j/84194144015 

Abstract:

Power/heat density becomes excessive in VLSI. Supply voltage in the current 7/10 nm process has been scaled to 0.7 V for logic devices to reduce dynamic power loss (Pdynamic  CwireVdd^2). The low supply voltage (Vdd), on the other hand, poses a challenge to static power loss (Pstatic = IoffVdd), because off-current (Ioff) is limited by the Boltzmann tail of the Fermi-Dirac distribution, corresponding to a minimum 60 mV/dec subthreshold swing SS at room temperature. To scale Vdd to 0.3 V while maintaining a 6 decades on/off ratio, transistors need to have a subthreshold slope (SS) < 60 mV/dec. The tunneling field effect transistor (TFET) is one technology that holds such promise as electron tunneling is not constrained by thermal statistics. Current state-of-the-art TFETs, however, have low on current (Ion) ≈ 10 µA/µm at Vdd = 0.3 V that precludes their applications in actual circuits. In this work, an InP-based triple heterojunction (3-HJ) TFET design is proposed to significantly increase Ion by exploiting a minimized tunneling distance, as well as resonant states in the 3-HJ. PNPN doping profile is employed in 3-HJ TFETs to eliminate the need for an ultra-thin body to ease processing. The simulated Ion reaches ≈ 300 µA/µm at Vdd = 0.3 V. To realize 3-HJ TFETs, three generations of device structures are tried. The main challenges come from the incompatibility between process modules within a small/limited process window. Among all device structures, the qualitative high-k/channel interface and gate metallization is important for high TFET performances. ALD post-metal H2 annealing is developed, and different gate metallization processes, including physical vapor deposition (PVD) of W, Ni, Al, Ti, and atomic layer deposition (ALD) of Ru, TiN, and TiN/Ru, are investigated. With the high-quality ALD TiN/Ru gate as well as the high-k/InP interface, a record low averaged SS of 68 mV/dec for long gate length devices, and a high peak transconductance of 0.75 mS/µm at VDS = 0.6 V in an 80 nm gate length InP channel planar MOSFET are demonstrated. Vertical InP channel MOSFETs and 3-HJ InGaAs/GaAsSb/InAs/InP TFETs with conformal TiN/Ru gate are fabricated using 3rd generation top-down planarization process. A high peak transconductance of 0.42 mS/µm in a 50 nm gate length vertical MOSFET at VDS = 0.6 V, which is comparable with planar MOSFETs at the same gate length, proves the process. The first demonstrated 3-HJ TFETs (having a gate length of 30 nm) show a strong short channel effect, and exhibiting SS of >80 mV/dec at VDS = 0.1 V, and Ion of ≈ 2 µA/µm at VDS = 0.3 V. The high SS and low Ion compared to simulation could be resulted from short channel effect, gate misalignment, reduced electric field at tunneling junction due to fringing field, and rough heterojunction interfaces given by a problematic epi. Negative differential resistance at VDS = 0.9 V, and high drain current under reverse drain bias are observed. A heterojunction interface trap-assisted tunneling model is used to explain those behaviors in 3-HJ TFETs.


Bio:

Hsin-Ying Tseng is a 5th year PhD student at UCSB working with Prof. Mark Rodwell on low power logic transistors. Before joining UCSB, she received her B.S. and M.S. in Electrical Engineering at NTHU (Taiwan) in 2016.

Hosted by: Professor Mark Rodwell
 
Submitted byHsin-Ying Tseng  <hsinying@ucsb.edu>