May 17 (Wed) @ 9:00am: "Machine Learning Empowered Agile Hardware Design and Design Automation," Nan Wu, ECE PhD Defense
With the ever-increasing applications comes the realization that efforts and complexity for developing hardware to keep pace with such compute demands are growing at an even faster rate. As the target cadence of Moore's law is already slipping, more burden is placed on the design methodology to achieve “equivalent scaling”. In this defense, I will introduce how intelligence is infused to empower agile hardware development and foster the virtuous cycle between hardware and ML. Hardware development involves many evaluation-optimization-verification iterations. Therefore, I will discuss how graph learning and deep reinforcement learning are applied for (1) fast and accurate design evaluation, (2) efficient and scalable design optimization, and (3) high-quality and productive design verification, with the ultimate goal to propel no-human-in-the-loop automation for scalable and efficacious hardware development flow.
Nan Wu is a Ph.D. candidate in the Department of Electrical and Computer Engineering (ECE) at the University of California, Santa Barbara, working with Prof. Yuan Xie. Her research interests reside in the joint area of computer architecture, electronic design automation, and machine learning (ML), aiming to facilitate agile hardware development empowered by ML. She received her B.S. degrees in Electronic Engineering and Economics from Tsinghua University in 2016, and the M.S. degree in ECE from UC Santa Barbara in 2018.
Submitted by: Nan Wu <firstname.lastname@example.org>