RESCHEDULED TO —>  June 7, (Wed) @ 9:00am: Extracting Reusable Primitives of Key-Value Operations and Finding Efficient Architecture Support,” Bangyan Wang, ECE PhD Defense

Date and Time
Zoom Meeting - Meeting ID: 982 462 6904 | Passcode: 4instPerCy

Zoom Meeting:


Architecture designs for data-parallel operations are widely available, such as SIMD on CPUs and SIMT on GPUs. While many applications have benefited from native program rewrites, the expressive power of composing SIMD-like primitives is limited by the inability to handle various complex cross-lane operations. Consequently, several applications, including scientific computing, database management, graph analysis, and genomic analysis, have not been able to fully leverage these advancements. On the other hand, domain-specific architectures offer more efficient utilization of silicon resources, but their widespread adoption is hindered by economic viability concerns, limiting their usage to a few specific areas. A more plausible approach involves identifying reusable operations that can be utilized across multiple domains and subsequently designing efficient architectures to support them.

This thesis focuses on the design and implementation of reusable parallel primitives for handling ordered and unordered (key, value) data structures. Initially, the motivation stemmed from a specific domain: sparse-sparse algebraic operations (such as SpGEMM), which struggled to benefit from existing SIMD or SIMT architectures. We present a streamlined solution to this problem, minimizing the instruction set architecture (ISA) and silicon area while ensuring efficiency.

As the research progressed, the design itself revealed its potential as a systematic approach to supporting ordered/unordered (key, value) operations, extending its applicability to a wide range of domains.


Bangyan is a Ph.D. candidate in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara, under the guidance of Professor Yuan Xie. His interests primarily revolve around the co-design of hardware architecture and sparse algorithms. He obtained his M.S. degree from UCSB in 2020 and his B.S. degree in Electrical Engineering from Tsinghua University in China in 2017.

Hosted by: Prof. Yuan Xie, Seal Group

Submitted by: Bangyan Wang <>