ECE Seminar Series – June 17 (Tue) @ 10:30am "Computing at the Limits in the Era of Artificial Intelligence," Naresh Shanbhag, Prof., ECE, UIUC
Location: Engineering Science Building (ESB), Room 2001
DISTINGUISHED LECTURE at the ECE SEMINAR SERIES
Abstract
Today’s computing platforms are challenged by emerging AI applications due to their high compute and data movement costs. These challenges revolve around operating at the limits of energy-accuracy-robustness trade-off intrinsic to decision-making systems implemented in nanoscale semiconductor processes. Traditional von Neumann architectures tend to aggravate these challenges due to the memory wall problem inherent in its structure. The slow-down in CMOS scaling per Moore’s Law complicates matters further. This talk will propose a model of computation based on Claude Shannon’s seminal work (1948) in determining the limits of communicating data in the presence of noise. The Shannon model of computation provides a formal approach to address the problem of energy efficient and robust deployment of AI workloads on computing platforms realized on nanoscale semiconductor fabrics that are pushed over the limits of reliable deterministic behavior into the stochastic domain. Such behavior can arise from deployment in harsh environments, e.g., space-based, or due to the use of emerging stochastic nanoscale devices, or due to SNR-aggressive efficiency-enhancing design methods, e.g., in-memory computing (IMC) and voltage overscaled digital circuits. The use of the Shannon model of computation will be illustrated in the context of IMC which currently is the state-of-the-art compute fabric, in terms of energy efficiency and compute density, for AI workloads. IMC architectures overcome the von Neumann bottleneck (“memory wall”) by embedding computation deep into the memory core (bitcell array) to minimize data access costs but at the expense of deterministic behavior. The deployment of AI models at scale, e.g., in today’s data centers introduces a new element into the mix viz. connectivity between compute nodes. Joint optimization of compute and connectivity is an open problem today requiring co-optimization of link components, e.g., forward error correction (FEC), within a distributed system thereby making the Shannon model of computation even more relevant. Our work on energy efficient FEC decoders for data center connectivity and the use of IMC for wireless massive MIMO connectivity, will be described briefly. The talk will conclude with a discussion of future opportunities in designing semiconductor-based computing platforms of the future.
Bio
Naresh R. Shanbhag is the Jack Kilby Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. He received his Ph.D. degree from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories at Murray Hill, NJ, where he led the design of the first high-speed transceiver chipsets for very high-speed digital subscriber line (VDSL), before joining the University of Illinois at Urbana- Champaign in August 1995. In 2000, Dr. Shanbhag co-founded and served as the Chief Technology Officer of the Intersymbol Communications, Inc., which introduced DSP-based mixed-signal ICs for electronic dispersion compensation of OC-192 optical links, and later became a part of Finisar Corporation in 2007. He has held visiting faculty appointments at the National Taiwan University (Aug.-Dec. 2007) and Stanford University (Aug.-Dec. 2014). His research focuses on the design of robust and efficient algorithms, VLSI architectures, and integrated circuit realizations for machine learning, communications, and signal processing. He has more than 200 publications in this area and holds thirteen US patents.
Dr. Shanbhag received a number of awards and honors including the 2024 SRC Innovation Award for the first patent on SRAM-based in-memory computing, the 2018 SIA/SRC University Researcher Award, the 2010 Richard Newton GSRC Industrial Impact Award, the 2006 IEEE Solid-State Circuits Society Best Paper Award, the 2006 Jewel of IRPS award, the National Science Foundation CAREER Award in 1996, and multiple best paper awards. From 2013-17, he was the founding Director of the Systems On Nanoscale Information fabriCs (SONIC) Center, a 5-year multi- university center funded by DARPA and SRC under the STARnet program chartered to develop next generation computing systems based on the Shannon model of computation. Presently he is on the leadership teams of the Joint University Microelectronics Program (JUMP) 2.0 Center for Co-Design of Cognitive Systems (COCOSYS) and the Center for Ubiquitous Connectivity (CUBIC) where he leads research themes on next generation AI algorithms and wireline/photonic connectivity, respectively. He is a Fellow of IEEE.
Hosted by: Distinguished Lecture at the ECE Seminar Series
Submitted by: Megan Ashley <mmashley@ucsb.edu>
