April 13 (Mon) @ 2:00pm: “Scaling, Stacking, and Cracking the Memory Wall,” Shyam Surthi, Distinguished Member of Technical Staff, Micron Technology

Location: Harold Frank Hall (HFH), Room 4108 (ECE Conf. Rm.)

Abstract

AI has exposed an inconvenient truth: computation is no longer the bottleneck — memory is. Despite decades of aggressive scaling, modern systems are increasingly limited by memory bandwidth, latency, energy, and data movement rather than transistor count. This seminar examines how conventional memory technologies can still be pushed and where fundamentally new ideas may be required.

We will trace the evolution of DRAM and NAND from classical scaling to today’s era of 3D architectures, extreme aspect ratios, and complex materials stacks. While innovations such as 3D NAND, high bandwidth memory, and advanced packaging have extended performance, they also introduce new limits driven by materials physics, reliability, variability, and thermal constraints. The central question is no longer can we scale, but what should we scale—and at what cost?  The talk concludes by highlighting challenges and opportunities at the intersection of materials, devices, and system architecture —inviting the next generation of researchers to help truly crack the memory wall.

Bio

Shyam Surthi is currently Distinguished Member of Technical Staff in Advanced NAND Technology team and currently based in Singapore.  He received BS and MS in Chemical Engineering from the University Institute of Chemical Technology (Mumbai, India) and Ph.D. in Electrical Engineering from the University of Alabama, specializing in processing and characterization of Perovskite materials. Subsequently, he was a Postdoctoral Fellow at North Carolina State University developing Si-molecular devices for memory applications.

Shyam joined Diffusion Process development at Micron in 2004, working on various film development projects and later transitioning to Advanced DRAM Process Integration role. Since 2011, Shyam has been in various people leadership roles in films process development for DRAM and emerging memory and technical leadership roles in NAND pathfinding with focus on integration. Shyam is a Senior Member of IEEE and holds 75 U.S. patents and several international patents.  He has >25 publications in refereed technical journals and conference proceedings.

Hosted & Submitted by: Kaustav Banerjee <kaustav@ece.ucsb.edu>