Feb 17 (Tue) @ 10:00am: "Potts-Model Probabilistic Hardware for Invertible Logic and Optimization," Jinesh Jhonsa, ECE PhD Defense

Location: Engineering Science Bldg (ESB), Room 2001 https://ucsb.zoom.us/j/83007185827?pwd=iflM7EE8ybvKY2e1YTCTzalb5N968Y.1
Research Area: Computer Engineering
Research Keywords: System Level Design, Probablistic computing, VLSI Design, Circuit Design

Abstract

Many problems central to modern computation, including combinatorial optimization, probabilistic inference, and constraint satisfaction, are inherently stochastic and asynchronous. In contrast, these problems are typically executed on deterministic, clocked von Neumann architectures that approximate randomness and relaxation through layered control and sequencing, leading to substantial energy and architectural overhead. This dissertation explores probabilistic computing as an alternative, using probabilistic bits (p-bits) to directly implement stochastic dynamics in hardware.

While prior p-bit systems have largely focused on binary Ising formulations, this work advances multi-state probabilistic architectures based on the Potts model. Potts nodes generalize Ising spins to q discrete states, enabling more compact representations of higher-order constraints and natural mappings to problems involving categorical variables. The dissertation focuses on a class of invertible logic problems and shows that a one-hot encoded Potts formulation maps directly to simple truth-table–based interactions, enabling efficient and interpretable hardware realizations.

A full-stack hardware–software co-design methodology is presented, spanning algorithm formulation, architectural mapping, and hardware implementation. Graph-coloring and update-scheduling strategies are developed to support parallel yet conflict-free stochastic updates, allowing large Potts networks to be efficiently deployed on reconfigurable hardware.

The proposed approach is demonstrated through a scalable FPGA implementation of Potts-based probabilistic networks, incorporating fixed-point stochastic updates, hardware-efficient annealing schedules, and piecewise-linear approximations of nonlinear activation functions. In addition, a mixed-signal CMOS prototype comprising 440 p-bits arranged in a Chimera network with on-chip annealing is fabricated, providing silicon-level validation of the architecture and enabling an exploration of hardware-aware learning techniques to mitigate analog mismatch.

The architectures and algorithms are evaluated on representative optimization and inference tasks, including integer factorization and invertible logic problems. Results from both FPGA and silicon demonstrate convergence behavior and solution quality consistent with theoretical expectations. Together, these contributions establish a practical and scalable framework for Potts-based probabilistic computing that connects stochastic algorithms, reconfigurable platforms, and custom silicon, offering a hardware-efficient path for future inference and optimization workloads.

Bio

Jinesh Jhonsa is a Ph.D. candidate in the Electrical and Computer Engineering Department at the University of California, Santa Barbara, advised by Prof. Luke Theogarajan. He received his M.S. in Electrical and Computer Engineering from the Georgia Institute of Technology and his B.E. in Electrical Engineering from the University of Mumbai, India. His research focuses on probabilistic computing, including p-bit and Potts-based architectures, FPGA implementations of large stochastic networks, and CMOS probabilistic hardware for inference and optimization.

Hosted By: ECE Professor Luke Theogarajan

Submitted By: Jinesh Jhonsa <jinesh@ucsb.edu>