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June 2 (Tuesday) @ 1:00pm: "Hardware-aware Probabilistic Computing for Combinatorial Optimization and beyond," M Mahmudul Hasan Sajeeb, ECE PhD Defense

Date and Time

Location: Harold Frank Hall (HFH), Room 4108 (ECE Conf. Rm.)
Zoom Links: https://ucsb.zoom.us/j/83512730346

Abstract

Probabilistic computing utilizes p-bits to solve complex combinatorial optimization problems, but scaling these Ising machines is severely bottlenecked by the dense, all-to-all connectivity required for real-world applications. This dissertation presents a holistic hardware-algorithm co-design framework to overcome these routing and frequency barriers.

First, we introduce a graph sparsification methodology using auxiliary variables to bound local connectivity. This decouples hardware frequency from system size, achieving O(1) frequency scaling compared to traditional O(1/N^2) degradation—validated through ASAP7 7-nm PDK and FPGA implementations. Second, we develop a Two-Dimensional Parallel Tempering (2D-PT) algorithm to resolve the tuning sensitivity introduced by sparsification, delivering orders-of-magnitude faster convergence on spin glass benchmarks without manual parameter tuning. Finally, we demonstrate the framework's practical efficacy on Massive MIMO detection. Our fully on-chip FPGA

Finally, we demonstrate the practical efficacy of this framework by targeting Massive Multiple-Input Multiple-Output (MIMO) detection. We report fully on-chip FPGA implementations of probabilistic solvers using both 1D-PT and 2D-PT architectures to accommodate varying antenna array scales. By embedding multiple parallel replicas of these sparsified networks onto a single device, the solvers achieve bit error rates significantly lower than conventional linear Minimum Mean Square Error (MMSE) detectors with rapid, millisecond-scale solution times. Ultimately, this work establishes a highly scalable path for probabilistic computers as domain-specific accelerators for dense optimization problems.

Bio

M Mahmudul Hasan Sajeeb is a Ph.D. candidate in the Electrical and Computer Engineering Department at UC Santa Barbara, advised by Prof. Kerem Y. Camsari. She earned her B.S. in Electrical and Electronic Engineering from the Bangladesh University of Engineering and Technology (BUET) in 2014 and her M.S. in EECS from UC Irvine in 2020. Her research focuses on hardware–algorithm co-design for probabilistic computing for combinatorial optimization and CMOS mixed-signal IC design.

Hosted By: ECE Professor Kerem Çamsari

Submitted By: M Mahmudul Hasan Sajeeb <msajeeb@ucsb.edu>