Sep 9 (Wed) @ 3:00pm: "Design and Implementation of High-Performance CMOS Low-Pass Filters for Biomedical and Communication Applications," Farzan Rezaei, ECE PhD Defense

Location: Engineering Science Bldg (ESB), Room 2001

Zoom Link: https://ucsb.zoom.us/j/86352704375

Abstract

The growing demand for multi-standard wireless communication and wearable and implantable biomedical systems has driven the need for high-performance, reconfigurable analog front ends. In wireless receivers supporting standards such as LTE, Wi-Fi, Bluetooth, and 5G, tunable low-pass filters (LPFs) play a critical role in channel selection and interference suppression. Similarly, LPFs are essential in biomedical front ends for extracting low-frequency physiological signals and suppressing unwanted interference and aliasing. Across these applications, achieving high linearity, low noise, low power consumption, and wide or tunable bandwidth remains challenging, particularly under the stringent area and scalability requirements of modern CMOS technologies.

This PhD research developed energy-efficient, high-linearity, low-noise, and tunable CMOS low-pass filters for wireless and biomedical applications. For biomedical signal processing, a fourth-order Gm-C low-pass filter was developed for ECG detection, achieving high linearity at a 0.5-V supply through a two-loop feedback architecture, body-driven transconductors, and current-mirror-based Gm stages. Fabricated in 0.18-µm CMOS, the prototype achieved below −40 dB HD3 for input amplitudes up to 340 mVpp, 154.7 µVrms integrated noise over a 240-Hz bandwidth, and a 53.6-dB dynamic range. For wireless applications, a passive charge-rotation switched-capacitor filter was developed using passive gain boosting, passive feedback, and pipeline operation to simultaneously improve gain, noise, linearity, and frequency scalability. Fabricated in 0.18-µm CMOS, the filter achieved a tunable cutoff frequency from 428 kHz to 6.75 MHz with 1.52-mW power consumption, while demonstrating competitive noise, linearity, and dynamic-range performance. In addition, a fifth-order hybrid low-pass filter combining a third-order switched-capacitor stage with a second-order source-follower-based stage was developed to achieve high linearity, low noise, and enhanced frequency selectivity. The fabricated 0.18-µm CMOS prototype provided a 4.1–39.7-MHz tuning range with 1.66-mW power consumption, 39.6/22.8-dBm IIP2/IIP3, 61.5-µVrms input-referred noise, 62.7-dB SFDR, and 75.4-dB 1% HD3 dynamic range. Collectively, these results demonstrate practical CMOS-compatible filtering techniques that enable high-performance, low-power, and reconfigurable analog front ends for emerging wireless and biomedical systems.

Bio

Farzan Rezaei began his Ph.D. program at the University of California, Santa Barbara, in January 2022. His doctoral research focuses on the design of analog and mixed-signal integrated circuits, including switched-capacitor and continuous-time filters, N-path filters, wideband receivers, and power amplifiers. In addition to his academic research, Farzan has gained industry experience through internship and cooperative positions, where he has worked on the design of data converters (ADCs/DACs), clock-management circuits (PLLs/DLLs), voltage and current regulators, and analog amplifiers.

Hosted By: ECE Professor Loai Salem

Submitted By: Farzan Rezaei’s Email