The semiconductor industry has been confronting an acute problem in the interconnect area. As IC feature sizes are scaled below 14 nm, copper wires exhibit significant “size effects” resulting in a sharp rise in their resistivity. This has adverse impact on IC performance and reliability in the form of higher communication costs due to increased interconnect delays and chip-level power dissipation, as well as due to reduced current carrying capacity of the copper wires. Carbon nanotubes (CNTs) have very high current carrying capability (at least two orders of magnitude higher than that of copper), long mean free path (on the order of μm), and high thermal conductivities (several times higher than that of copper), indicating that CNTs could be potentially employed as alternative materials for next-generation nanoscale interconnects. Such interconnects can enhance the electrical performance as well as eliminate reliability concerns that plague nanoscale copper interconnects.
However, fabrication and characterization of long and horizontal CNT-bundles necessary for interconnect applications have remained an enigma. In a game-changing development, ECE researchers led by Prof. Kaustav Banerjee in collaboration with NASA Ames and TU-Munich have demonstrated a novel process that, for the first time, enables fabrication of high-density, long (over 100 microns) and thick (up to microns) horizontally aligned CNT interconnects. This demonstration has thus overcome one of the biggest challenges facing the CNT interconnect technology and is a vital step for implementation of CNT based interconnects and passive devices in next-generation VLSI. The developed process not only yields horizontal CNT interconnects with the lowest reported resistivity, but also enables the first ever fabrication of a CNT based on-chip spiral inductor. These results have been recently published in the IEEE Transactions on Electron Devices by ECE alum Dr. Hong Li et al.