ECE Ph.D. candidate Junkai Jiang and co-authors receive the 2018 IEEE S3S Best Student Paper Award

October 30th, 2018

photos of jiang, parto and cao
Jiang and co-authors demonstrate for the first time that 3D chips made with 2D materials can achieve 10-folds higher integration density as compared to conventional electronic materials at the 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) held in San Francisco, CA

The technical program committee of the conference presented the Best Student Paper Award to Jiang from Professor Kaustav Banerjee’s Nanoelectronics Research Lab (NRL) for the selected paper “Monolithic-3D Integration with 2D Materials: Toward Ultimate Vertically-Scaled 3D-ICs.” The paper was published in the 2018 Proceedings of the IEEE S3S and is co-authored by Professor Banerjee and two other NRL members – Kamyar Parto, a second year ECE graduate student and Dr. Wei Cao, a post-doctoral fellow. While the article is not yet available on IEEE Xplore, a discussion of the work can be found in a recent invited article on 2D materials from the NRL co-authored by Cao, Jiang, et al., in the October 2018 issue of the IEEE Transactions on Electron Devices.

The semiconductor industry has been looking for alternative 3D IC technology solutions, particularly monolithic 3D integration that promises higher integration density and better performance compared to conventional methods including the Through-Silicon-Via (TSV)-based 3D ICs that are currently in the market. However, monolithic 3D integration with conventional electronic materials faces several challenges including thermal, electrical, and process issues. Jiang and co-authors demonstrate through detailed modeling and simulation, why atomically-thin (2D) layered materials provide a better platform, with respect to bulk materials (such as Si, Ge, GaN, etc.), for realizing ultra-high-density monolithic 3D-ICs for next-generation electronics.

Over the past several decades the IEEE S3S Conference has developed into one of the most relevant venues and a hot spot for the latest research and deliberations on state-of-the-art technology topics including 3D Integration, Ultra-Low Power Circuits and Devices, and Silicon-on-Insulator (SOI) Technology.

Jiang’s doctoral research is focused on modeling, design, synthesis, and characterization of novel interconnect structures and materials. Professor Banerjee is widely regarded as one of the key visionaries behind the 3D IC technology being employed by the semiconductor industry for continued scaling and integration beyond Moore’s law, and led the research.

IEEE S3S Conference

IEEE Transactions on Electron Devices article

Nanoelectronics Research Lab (NRL)