Programmable Probabilistic Computer with 1,000,000 p-bits

How a UC Santa Barbara team networked 18 chips into the first million p-bit computer, then found a simple rule for when distributed hardware behaves as one

Project PI: Kerem Çamsarı, Prof. ECE, Computer Engineering

Running today's artificial intelligence (AI) models consumes large amounts of electricity, most of it spent on enormous numbers of arithmetic operations. An alternative is to let the physical behavior of the hardware carry out part of the computation. This is the idea behind probabilistic computers, which are built from p-bits: circuits that fluctuate between 0 and 1 and solve problems by drawing samples rather than by exhaustive calculation. That makes them well matched to the sampling, optimization, and inference that power much of machine learning. Their main limitation has been scale, because a probabilistic computer had never grown beyond a single chip, held back by that chip's capacity and memory bandwidth.

A team in the OPUS Lab at UC Santa Barbara has now crossed that line, building the first probabilistic computer to reach one million p-bits. The group networked 18 chips into a single machine far bigger than any one of them could hold. It runs a trillion p-bit updates per second, keeps every coupling weight in on-chip memory, and lets neighboring chips exchange only single-bit boundary states. IEEE Spectrum featured the machine as the largest probabilistic computer to date. The machine did not appear overnight. The first prototype, built from two field-programmable gate arrays (FPGAs), ran in 2023. A six-FPGA rack followed in 2024, and the 18-FPGA million p-bit system came together in 2025 on a commercial emulation platform during a collaboration with Siemens. The surprising part was how gracefully the divided machine tolerated letting its shared boundary information fall out of date. “What surprised us was how forgiving these machines are,” said Kerem Y. Çamsarı, the principal investigator. “As long as the chips refresh their shared boundaries quickly enough, the whole system behaves like a single machine, and when we deliberately push it faster than that it degrades gently rather than breaking.”

That behavior is governed by one quantity: the ratio between how often neighboring chips exchange boundary information and how often each p-bit updates. Above a threshold set by how the problem is mapped onto the hardware, the distributed machine matches a golden reference run on a graphics processing unit (GPU). Below it, solution quality falls off gradually, turning parallelism into a controlled trade between speed and accuracy. A theoretical model reproduces the same behavior, so the effect of splitting a computation across chips can be predicted before the hardware is built. Reaching that clean rule took years of trial and error. “This took years, and a lot of architectures that broke at scale, before one finally held together,” said Navid Anjum Aadit, the doctoral researcher who led the work. “Getting a million p-bits to behave as one machine, and still speed up when we pushed it, made all of it worth it.”

Across very different hard problems, the machine holds up. It runs hard spin-glass problems at full scale, tackles large satisfiability (SAT) formulas, and reached the certified-optimal solution to a classic graph-optimization benchmark that had stood open since 2000, a solution first found by a separate algorithm in 2025. Its use is not limited to optimization. Because a p-bit is a general-purpose probabilistic building block, related p-computing work has already gone further: sampling the quantum states of many-body systems, decoding signals in large wireless antenna arrays, generating structured data for diffusion-style models, and identifying the most relevant terms in the attention layers that dominate today's AI. “This hardware is usually classified as optimization hardware, which understates it,” Aadit said. “It is really a general-purpose tool for computing with probability.” The million p-bit system is a testbed, not a finished product. It was built at scale to expose the design constraints that future low-power hardware must solve. A companion seven-nanometer physical-design study already projects that a single partition would fit in 0.66 square millimeters at about 248 milliwatts, pointing toward far leaner implementations. “The goal is to let the physics carry out the computation,” said Çamsarı. “As the power demands of AI rise, the real question is whether hardware based on randomness can outperform conventional machines in cost and speed on the tasks it suits.”

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