http://www.ece.ucsb.edu/courses/ECE122/122_F14Banerjee/    Course Info |  Lecture Notes | Homework | Labs | Project | Resources   - ECE 122A - VLSI Principles    University of California, Santa Barbara, Fall Quarter 2014 - Instructor: Prof. Kaustav Banerjee    kaustav (at) ece.ucsb.edu    Office: Harold Frank Hall (HFH) 4151    Phone: (805) 893-3337    Fax: (805) 893-3262 - Teaching Assistant: Junkai Jiang    junkaijiang (at) ece.ucsb.edu    Office: HFH 2164 - Lecture Location : ESB 1003 - Lecture Time: Tue. & Thu. 3:30-4:45 PM - Lab Location: HFH 1140 (Map) - Lab Time: Tue. 8:00-10:50 AM - Professor Office Hour Location: HFH 4151 - Professor Office Hour Time: Fri. 1:00-2:00 PM - TA Office Hour Location:  HFH 2164 - TA Office Hour Time: Tue. 10:00 AM - 11:30 AM - More course info - Midterm Exam: Thursday, November 13, 3:30-5:30 PM   One-Page 'Cheat Sheet' is allowed. - Final Exam: Thursday, December 18, 4:00 - 7:30 PM   A two-Page A4 size 'Cheat Sheet' is allowed. Textbook CMOS VLSI DESIGN 4th Edition     - Lecture 01 (10/02/2014) - Introduction - Lecture 02 (10/09/2014) - Overview of IC - Lecture 03 (10/14/2014) - Static CMOS Design - Lecture 04 (10/16/2014) - CMOS Fabrication Process, Layout and Design Rules - Lecture 05 (10/21/2014) - Semiconductor Physics - Lecture 06 (10/23/2014) - P/N Junction and MOS Structure - Lecture 07 (10/28/2014) - MOSFET - Lecture 08 (10/30/2014) - MOSFET and Inverter - Lecture 09 (11/04/2014) - Inverter - Lecture 10 (11/06/2014) - Inverter Sizing - Lecture 11 (11/18/2014) - Interconnect - Lecture 12 (11/20/2014) - Combinational Logic Circuits   Reference: K. Banerjee, "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs", IEEE TED, 2002 - Lecture 13 (11/24/2014) - Datapath (Adder, Multiplier and Shifter) - Lecture 14,15 (11/25/2014) - Ratioed Logic, Dynamic Logic   Reference:   Dadgour H F, Banerjee K. "A novel variation-tolerant keeper architecture for high-performance low-power wide fan-in dynamic OR gates", IEEE Transactions on VLSI, 2010 - Lecture 16,17 (12/2/2014) - Sequential Logic Circuits - Lecture 18,19 (12/4/2014) - Semiconductor Memories   Reference:   W. Cao et al., "Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory?" IEEE Transactions on Electron Devices, Oct 2014 - Homework 1 (Due on Thursday, 10/16/2014, 5:00 PM) - Review of Digital Design   References:   G. E. Moore, "Cramming more components onto integrated circuits," Electronics Magazine, pp. 114-117, 1965.     Solutions - Homework 2 (Due on Friday, 10/24/2014, 5:00 PM) - CMOS and Pass Transistors     Reference on Silicon Process:   Intel, "From Sand to Circuit"   Intel, "From Sand to Silicon"   Solutions - Homework 3 (Due on Friday, 10/31/2014, 5:00 PM) - Semiconductor Physics   Solutions - Homework 4 (Due on Monday, 11/10/2014, 5:00 PM) - MOSFET and CMOS Inverter   Solutions - Homework 5 (Due on Monday, 11/24/2014, 5:00 PM) - CMOS Sizing, Interconnect   Solutions - Homework 6 (Due on Friday 12/05/2014, 5:00 PM) - Logic Design Styles   Solutions - Homework 7 (Due on Friday 12/12/2014, 5:00 PM) - Sequential Logic and Memory   Solutions - Do NOT - Do not copy from each other! - Homework Box is at HFH 3120 - Lab 1 (Due on Tuesday, 10/14/2014, 5:00 PM) - Environment setup and tool practice    For remote access to your Linux account, please refer to the appendix:    Lab1_Appendix.pdf - Lab 2 (Due on Tuesday, 10/21/2014, 5:00 PM) - HSpice practice - Lab 3 (Due on Friday, 10/31/2014, 5:00 PM) - Single-Stage Logic Gate Layout - Lab 4 (Due on Wednesday, 11/19/2014, 5:00 PM) - Inverter VTC, CMOS Sizing and Delay - HSpice MOS Model Libraries: http://ptm.asu.edu/ - You will need to use these software: (Manuals provided) - HSpice (Circuit Netlist Simulation) - HSpice Manual - CosmosScope/AvanWaves    (Waveform viewer for Linux/Windows) - MMI MAX - MMI SUE - CScope Manual - AvanWaves Manual - MAX Tutorial - SUE Tutorial - Lab reports should be handed in to homework box. - Warning: DO NOT make copies of these manuals!   Project Reference:    LVS Technology for the Intel(R) Pentium(R) 4 Processor on 90nm Technology - Final Project - PART 0   Work either individually or in a group of two.   Please sign up in the Group List. - PART 1 Review on LVS Technology (Due on Monday 11/17/2014 5:00 PM) - PART 2 (Due on Friday 11/21/2014 5:00 PM) - PART 3 (Due on Wednesday 12/03/2014 5:00 PM) - PART 4 (Due on Friday 12/12/2014 5:00 PM) - Final Report due on Saturday, 12/20/2014, 10:00 PM - Oral Exam to be announced ... - An Introduction to GNU/Linux Command Shell:   http://vic.gedris.org/Manual-ShellIntro/1.2/ShellIntro.pdf - For a better understanding of device physics, please refer to the supplementary textbook:    Modern Semiconductor Devices for ICs (1st Edition), by Chenming Hu - Midterm of 2013 Fall   Solution to 2013 Fall Midterm - Solution to 2014 Fall Midterm

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Nanoelectronics Research Lab