http://www.ece.ucsb.edu/courses/ECE122/122_F23Banerjee/ https://tinyurl.com/4frr3txy

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- ECE 122A - VLSI Principles
   University of California, Santa Barbara, Fall Quarter 20
23

- Instructor: Prof. Kaustav Banerjee
   kaustav (at) ece.ucsb.edu   

- Teaching Assistant: Ankit Kumar
   ankitkumar (at) ece.ucsb.edu
   Office: HFH 2164

- Lecture Location:  ESB 1003 (Cooper Lab)
- Lecture Time: Tue. & Thu. 3:30-4:45 PM

- Lab Location: ENGR1 1140 (ECI Lab)
-
Lab Timings: Tue. 8:00-10:50 AM

- Professor Office Hour Location: Room 4151, HFH
- Professor Office Hour Time:  (Appointment by email)

- TA Office Hour Location: HFH 2164
- TA Office Hour Time: Wednesday 3:30-4:30 PM

- More course info

- Midterm (2022) Paper, Solutions


Textbook
CMOS VLSI DESIGN
4th Edition

 

 


- Lecture 01 (9/28/2023) - Introduction
- Lecture 02 (10/3/2023) -
History of transistors and ICs/Switch-level understanding of static CMOS circuits
- Lecture 03 (10/5/2023) - Switch-level logic circuits
- Lecture 04 (10/10/2023) - Review of Semiconductor physics
- Lecture 05 (10/12/2023) - P/N Junctions and MOS Structure
- Lecture 06 (10/17/2023) - MOS Physics and Operation
- Lecture 07 (10/24/2023) - Dynamic Behaviour of MOSFET and CMOS Inverter
- Lecture 08 (10/26/2023) - Inverter
- Lecture 09 (11/02/2023) - Inverter Sizing and Logical Effort
- Lecture 10 (11/07/2023) - Designing Combinational Logic Circuits
- Lecture 11 (11/09/2023) - Interconnects
- Lecture 12 (11/16/2023) -Ratioed Logic
- Lecture 13 (11/21/2023) - Adders and Datapath
- Lecture 14 (11/28/2023) - Sequential Logic
- Lecture 15 (11/30/2023) - Memories I
- Lecture 16 (12/05/2023) - Memories II


- Homework 1 (Due on Monday, 10/09/2023, 5:00 PM) - Review of Digital Design
- Solutions
- Homework 2 (Due on Tuesday, 10/17/2023, 5:00 PM) - IC Fabrication, CMOS and Pass Transistors
- Solutions
References:
Intel, "From Sand to Circuit"
Intel, "From Sand to Silicon"
Video 1 - Silicon Run 1
Video 2 - Silicon Run II

- Homework 3 (Due on Friday, 10/27/2023, 5:00 PM) - Semiconductor Physics, IC Fabrication, P/N Junctions and MOSCAP
- Solutions

- Homework 4 (Due on Monday, 11/06/2023, 5:00 PM) - MOSFET and CMOS Inverter
- Solutions

- Homework 5 (Due on Friday, 11/24/2023, 5:00 PM) - MOSFET, CMOS Sizing, Logical Effort, Ratioed and Pass Transistor Logic
- Solutions

- Homework 6 (Due on Tuesday, 12/05/2023, 5:00 PM) - Interconnects, Dynamic and Sequentail Logic
- Solutions

- Homework 7 (Due on Monday, 12/11/2023, 5:00 PM) - Sequential Logic, Adder, Memory
- Solutions
- Lab 1 (Due on Thursday, 10/12/2023, 5:00 PM) - Environment setup and tool practice
- Lab 2 (Due on Thursday, 10/19/2022, 5:00 PM) - CMOS circuit simulation with HSpice
- Lab 3 (Due on Thursday, 10/26/2022, 5:00 PM) - Single-stage logic gate CMOS layout
- Lab 4 (Due on Thursday, 11/16/2022, 5:00 PM) - Inverter, CMOS sizing and delay

Additional files for Lab 1

  180nm_bulk.txt
  bash_configure
  inv.sp

- You will need to use these software: (Manuals provided)
- HSpice (Circuit Netlist Simulation) HSpice Manual
- CosmosScope/AvanWaves
   (Waveform viewer for Linux/Windows)
- MMI MAX
- MMI SUE

CScope Manual
AvanWaves Manual
MAX Tutorial
SUE Tutorial

Project Reference:
 LVS Technology for the Intel(R) Pentium(R) 4 Processor on 90nm Technology
 Spice Model (90 nm)

- Final Project
- PART 0
Work either individually or in a group of two.
Please sign up in the Group List.

- PART 1 Review on LVS Technology (Due on Friday 12/01/2023 5:00 PM)

- PART 2 (Due on Tuesday 12/05/2023 5:00 PM)

- PART 3 (Due on Saturday 12/09/2023 5:00 PM)

- Final Report (Due on Tuesday 12/12/2023 11:59 PM)
- An Introduction to GNU/Linux Command Shell:
  http://vic.gedris.org/Manual-ShellIntro/1.2/ShellIntro.pdf

- For a better understanding of device physics, please refer to the supplementary textbook:
   Modern Semiconductor Devices for ICs (1st Edition), by Chenming Hu

- Midterm Solutions

 

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Last Update: 2022
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